IEEE

13.5 A 64Gb/s/pin PAM4 Single-Ended Transmitter with a Merged Pre-Emphasis Capacitive-Peaking Crosstalk-Cancellation Scheme for Memory Interfaces in 28nm CMOS

Abstract: With the development of massive computing and AI technologies, the memory interface is critical to achieve higher computational throughput. Increasing the parallel-channel density is an ...
IEEE

50Gb/s high-speed serial interface receiver CTLE equalization circuit design

Abstract: In high-speed interface circuits, a continuous-time linear equalizer (CTLE) is typically used at the receiving end to eliminate the effect of intersymbol interference (ISI) on signal ...
C&EN

Thermal Stability and Mechanical Toughness of Laminated Perovskite Solar Cells

Materials Science and Engineering Program, University of California, San Diego, La Jolla, California 92093, United States Aiiso Yufeng Li Family Department of Chemical and Nano Engineering, University ...
C&EN

Dictating Excited State Pathways at the Perovskite Nanocrystals–NIR Dye Interface by Thermodynamics-Governed Kinetics

Key Laboratory of Photochemical Conversion and Optoelectronic Materials, Technical Institute of Physics and Chemistry Chinese Academy of Sciences, Beijing 100190, China University of Chinese Academy ...