Semiconductor Engineering

Systematic Training and Validation of AI-based Systems With Digital Twins and Scenario Engineering

A new technical paper, “Towards Structured Training and Validation of AI-based Systems with Digital Twin Scenarios,” was published by researchers at RWTH Aachen University and RIF e.V. Abstract ...
Semiconductor Engineering

Research Bits: Mar. 17

But now, with this new platform, we can create thousands of individually controllable laser beams that can interact with the ...
Semiconductor Engineering

Optimizing Oxide Interfaces To Preserve Device Performance in TMDC-based Transistors (imec, ETH Zurich)

A new technical paper, “Oxide induced degradation in MoS2 field-effect transistors,” was published by researchers at imec and ETH Zurich. Abstract excerpt “Transition Metal Dichalcogenides (TMDC) are ...
Semiconductor Engineering

How AI Will Automate Chip Design

AI has been used in EDA for many years for the core algorithms in tools, but it’s getting smarter and more optimized with the rollout of generative and agentic AI. As it evolves and improves, hardware ...
Semiconductor Engineering

Pathfinding Method That Models ECC Overhead for Chiplet Interconnects (UCLA)

A new technical paper, “Link Quality Aware Pathfinding for Chiplet Interconnects,” was published by researchers at UCLA. Abstract “As chiplet-based integration advances, designers must select among ...
Semiconductor Engineering

3D DRAM with CBA Technology (Georgia Tech)

Technology Co-Optimization of Bitline Routing and Bonding Pathways in Monolithic 3D DRAM Architectures,” was published by researchers at Georgia Tech. Abstract “3D DRAM has emerged as a promising ...
Semiconductor Engineering

AI Design Reshapes Data Management

Integrating AI into chip workflows is pushing companies to overhaul their data management strategies, shifting from passive storage to active, structured, and machine-readable systems. As training and ...
Semiconductor Engineering

CPO Is Extending The Limits Of What’s Possible In AI Data Centers

AI data centers are starting to replace copper with co-packaged optics in an effort to reduce energy consumed per bit and ...
Semiconductor Engineering

Scale-Up, Scale-Out Get a New Partner

Three AI data center scaling strategies are scale-up, scale-out, and scale-across. Scale-up is within a rack; scale-out is ...
Semiconductor Engineering

Auto Security Accelerates With Standardization And Certified Silicon

OEMs are driving faster design cycles and enhanced security amid evolving vehicle architectures and compliance requirements.
Semiconductor Engineering

Rethinking Voice AI At The Edge: A Practical Offline Pipeline

Cloud-based AI dominates the headlines, but responsive and private interaction lies at the edge. This blog post shows how to build a fully offline, real-time voice assistant using the Arm-based NVIDIA ...
Semiconductor Engineering

Human-Centered Agentic AI Comes To RTL Verification

The long-term objective is to let engineers spend more time on what really matters and less time on manual coordination.